EMPC23

The course will explain the evolution of two types of materials used in semi-conductor packaging –Die Attach adhesives and Liquid Molding compounds.

Die attach technology has been largely unchanged for several decades, using silver filled thermosetting resins (typically epoxy or bismaleimide) to attach semiconductor die, and curing at around 150ºC to 175ºC. However, recent developments in commercial, automotive and industrial
electronic devices are driving changes – in two opposing directions.

The move towards higher power ratings seen in Electric Vehicles & Renewable Energy devices demands improved thermal conductivity. This is mirrored in the need for better electrical conductivity for high frequency (RF & microwave) applications. Furthermore, automotive requirements for extended operating lifetimes in harsh environments are imposing additional reliability requirements. Traditional adhesives and solder are unable to meet these new
requirements, and the industry is moving towards sintering adhesives. Some are almost pure metal, requiring pressure during cure, and some contain small amounts of resin to enable Pressureless processing.

By contrast, commercial devices (eg mobile phones etc), increasingly use plastics in their construction, requiring adhesives that cure at low temperature. Operating conditions are not so harsh as automotive applications, but high speed processing is essential.

So the development of adhesives is following two different approaches to achieve these conflicting needs.

The second part of the course explains liquid encapsulation materials. Formulations have been optimized for “Chip on Board” applications and for Underfill applications, and the different properties of uncured & cured materials will be explained. In addition, on-going tightening of
environmental regulations – particularly in European region – are driving re-formulation of many traditional products.

Liquid Encapsulants have been developed that can be applied by Compression Molding and/or stencil printing. These enable coating or isolation layers to be created with increasingly large areas; and also the fabrication of 5 and 6 side protection layers on small components.

Although new materials are often aimed at specific markets and applications, their properties can frequently make them suitable for use in emerging & creative areas.

Chiplet is a chip design method and heterogeneous integration is a chip packaging method. Chiplet design and heterogeneous integration packaging have been generated lots of tractions lately. For the next few years, we will see more implementations of a higher level of chiplet designs and heterogeneous integration packaging, whether it is for cost, time-to-market, performance, form factor, or power consumption. In this lecture, the following topics will be covered.

• System-on-Chip (SoC)
• Why Chiplet Design?
• Chiplet Design and Heterogeneous Integration Packaging – Chip Partition and Chip Split
  • Chip partition and Heterogeneous Integration
  • Chip split and Heterogeneous Integration
  • Advantages and Disadvantages
• Lateral Communication between Chiplets (e.g., Bridges)
  • Bridge Embedded in Build-up Package Substrate
  • Bridge Embedded in Fan-Out EMC with RDLs
  • UCIe
  • Hybrid Bonding Bridge
• Fan-Out Wafer/Panel-Level Packaging
• Chiplet Design and Heterogeneous Integration Packaging – Multiple System and Heterogeneous Integration (MSHI)
  
  • MSHI with Package Substrate (2D IC Integration)
  • MSHI with Thin Film layer on the Package Substrate (2.1D IC Integration)
  • MSHI with TSV-less (Organic) Interposer (2.3D IC Integration)
  • MSHI with Passive TSV-Interposer (2.5D IC Integration)
  • MSHI with Active TSV-Interposer (3D IC Integration)
• Summary
• Potential R&D Topics in Chiplet Design and Heterogeneous Integration Packaging

A Power Electronics Packaging Professional Development Course is proposed to provide a thorough understanding of the processing steps involved in the manufacture of power electronics components and modules.

Power Electronics Packaging determines the performance, reliability and costs of power modules and is often overlooked at the design process stage. Knowledge of the materials and assembly processes resides within a limited cohort of electronics packaging engineers and there is little visibility of the multi-disciplinary nature of the work at schools/colleges and Universities.

One of the most significant challenges will be the achievement of reliable and fully functional products that will require electronic and electrical packaging solutions that can operate at higher currents and voltages, faster frequencies and increased temperatures, which will place increasingly severe demands on the materials and assembly processes.

This course will go through the process steps starting from the semiconductor wafer through to the finished module, with information supplied on:

• Packaging and Assembly Processes
• Material, Manufacturing and Test Costs
• Value added during the Packaging and Assembly steps

Wafer Level Packaging (WLP) combined with Redistribution Layer (RDL) generation, is a well-developed technology for the realization of Fan-in structures for miniaturized FlipChip packages on dense Printed Circuit Board (PCB) based packages.

For these RDLs high performance photosensitive polymers like PI, PBO and BCB are developed; allowing for reliable thin film layer stacks under the solder ball interconnects between the CTE mismatched silicon dies and PCB. The development of the Fan-out Wafer Level Packaging on Epoxy Molding Compound (EMC) wafer substrate sets new demands on the wafer level process.                                                                                                                       

The embedding of single dies allows for miniaturized packages with shortest interconnects. While embedding of multiple dies leads to complete system in packages where a high density thin film multi-layer routing connects different components which was typically done by the PCB before. The EMC substrate form factor is not limited to wafer size, which enables upscaling of the WLP to larger formats.

Here, Panel Level Packaging (PLP) is one of the latest trends in microelectronics packing. Besides technology development towards heterogeneous integration including multiple die packaging as described before, passive component integration in package and redistribution layer or package-on-package approaches and also larger substrates formats are targeted.

Manufacturing is currently done on wafer level up to 12”/300 mm and 330 mm respectively. For higher productivity and therewith lower costs larger form factors are introduced. Instead of following the wafer level roadmaps to 450 mm, PLP might be the next big step. PLP has the opportunity to adapt processes, materials and equipment from other technology areas. PCB, Liquid Crystal Display (LCD) or solar equipment is manufactured on panel sizes and offer new approaches also for PLP. However, an easy upscaling of technology is not possible when moving from wafer to panel level. Materials, equipment and processes have to be further developed or at least adapted.

The PDC will give a status of the current Fan-in and Fan-out Wafer Level Packaging as well as Panel Level Packaging. This will include material discussion, technologies, applications and market trends as well as cost modelling.